1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to an IC tester having a programmable formatter for providing a wide range of drive and compare format.
2. Description of Related Art
A typical per-pin integrated circuit tester includes a pattern generator and a set of tester channels, one for each pin of an integrated circuit device under test (DUT). The tester organizes a test into a set of successive test cycles, and during each test cycle each channel carries out a test activity at a corresponding DUT pin. For example a tester channel may supply a test signal input to the DUT terminal or may monitor a DUT output signal at the terminal and produce an indicating "FAIL" signal when the DUT output signal does not behave as expected.
The tester includes a pattern generator for supplying "formatset" data (FSET), "timeset" data (TSET) and reference data (PG) to each tester channel for each test cycle. The FSET data references a particular drive or compare format the channel is to use during the test cycle. A "drive format" is a particular manner in which the channel controls the states of its output test signal during the test cycle. A "compare format" is a particular manner in which the channel determines whether the DUT output signal is behaving as expected during the test cycle. The TSET data indicates certain times during a test cycle at which an event is to occur, such as for example, a test signal state change or a DUT output signal comparison. The PG data can be used to indicate desired states of the test signal or expected states of the DUT output signal.
A typical tester channel includes a pin electronics circuit for generating the test signal at the DUT in response to a set of drive control signals indicating the test signal state (high, low or tristate). The pin electronics circuit also monitors the DUT output signal at the terminal and produces compare high (CH) and compare low (CL) signals indicating whether the DUT output signal is currently above a high logic level or below a low logic level. In addition to a pin electronics circuit, each tester channel also includes one or more timing signal generators and a formatter circuit. Each timing signal generator receives the TSET data from the pattern generator at the start of each test cycle and produces a timing signal pulse input to the formatter circuit at a time during the test cycle indicated by the TSET data. The formatter circuit receives the FSET data from the pattern generator at the start of each test cycle and generates the drive control signal inputs to the pin electronics circuit, causing it to carry out a drive format indicated by the FSET data. The formatter may use the PG data to determine the states of the drive control signals and uses the timing signals as references when producing state changes in the control signals. The formatter circuit also samples the compare high CH and CL outputs of the pin electronics circuit to determine whether to assert the FAIL signal during the test cycle using a compare format also referenced by the FSET data. Depending on the compare format specified, the PG data may reference expected states of the CH and CL data. The timing signals indicate when the formatter is to sample the CL and CH data.
As illustrated in FIG. 7, a typical prior art formatter includes a logic circuit 2 receiving the T1, T2, PG and FSET data and producing a set of four output signals applied to set and reset inputs of a pair of flip-flops 3A and 3B. Flip-flop 3A produced the D drive signal and flip-flop 3B produces the Z drive signal. The FSET data references one of a limited set of D and Z drive signal formats that the formatter may produce during the test cycle. In particular the FSET data indicates the number (0-2) of state changes the D and Z signals are to undergo during the test cycle and indicates whether each state change is to occur on the edge the T1 or T2 signal. The drive signal format referenced by the FSET data also indicates whether logic circuit 2 is to use a bit of the PG data as a reference to indicate the state to which a D or Z signal is to change.
The FSET data may alternatively reference a compare format. When the tester channel is to carry out a compare operation, the PG data may indicate expected states of the CH and CL data. Depending on the compare format selected, the formatter circuit may sample the CH and CL data on an edge of one of the T1 or T2 timing signals or may monitor the CH and CL data during a window of time between the T1 and T2 signals. The prior art formatter includes another logic circuit 4 which process the PG and FSET data to produce signals for controlling operations of a window comparator 5 and an edge comparator 6. When enabled by control data from logic circuit 4, window comparator 5 monitors the CH and CL data from the DUT and asserts and output FAIL signal via an OR gate 7 when the CH and/or CL data passes through unexpected states at any time during a window of time bounded by the T1 and T2 timing signals. When edge comparator 6 is enabled by signals from logic circuit 4, it asserts the FAIL signal via OR gate 7 when CH or CL is of an unexpected state upon receiving an edge of the T1 or T2 signal.
Since the FSET data input to the formatter selects a particular drive or compare format, and since that FSET data has only 4 bits, it can only select one of sixteen drive or compare formats because a 4-bit word has only sixteen different values. The nature of the 16 different formats is determined by the design of logic circuits 2 and 4. Thus prior art logic decoders 2 and 4 are specifically designed to provide the drive and compare formats that will be needed for the types of tests that the tester is expected to perform. Accordingly, when designing a test for an integrated circuit, a user must take into account the limited number of available drive and compare formats. The user cannot specify drive or compare formats that are not designed into logic circuit 2 or 4.
The formatter architecture of FIG. 7 makes rather inflexible use of its input data when providing drive and compare formats, and therefore provides only a limited number of drive and compare formats. What is needed is a formatter for an integrated circuit tester that is highly flexible in the manner in which it uses input data and timing signals to produce drive and compare formats so that it provides a much larger number of useful drive and compare formats and allows a user the flexibility to design test formats to be employed.